The present invention relates to semiconductor packages, and more particularly, but not .by way of limitation, to semiconductor packages with increased solder joint strength for mounting the semiconductor package to external surfaces.
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal leadframes for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the leadframe are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package therein described incorporates a leadframe as the central supporting structure of such a package. A portion of the leadframe completely surrounded by the plastic encapsulant is internal to the package. Portions of the leadframe extend internally from the package and are then used to connect the package externally. More information relative to leadframe technology may be found in Chapter 8 of the book Micro Electronics Packaging Handbook, (1989), edited by R. Tummala and E. Rymaszewski, and incorporated by reference. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1xc3x971 mm to 10xc3x9710 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are generally manufactured in the same manner.
Such conventional semiconductor packages are not without certain problems.
Specifically, in a typical semiconductor package the bottom surface of the externally exposed leads is flat. The flat bottom surface of these externally exposed leads results in a weakening of the solder joint strength between the semiconductor package and an external surface, such as that of a motherboard. When the semiconductor package is mounted onto a motherboard or other surface by soldering, the flat bottom surface of the leads may lack enough friction to readily maintain a sufficient solder joint strength. As a result, the semiconductor package may undesirably detach from the motherboard at one or more critical locations. This is extremely undesirable and is a distinct disadvantageous aspect of prior art designs. The present invention addresses such problems by providing semiconductor packages with increased solder joint strength.
The present invention relates to semiconductor packages. More particularly, one aspect of the present invention comprises a semiconductor chip having an upper surface and a bottom surface in conjunction with the following features of the invention. A plurality of input bond pads and output bond pads on the upper surface of the semiconductor chip and along the circumference of the semiconductor chip are electrically connected to the semiconductor chip. A chip paddle is provided which has a top surface, a side surface and a bottom surface. The chip paddle, being bonded to the bottom surface of the semiconductor chip by an adhesive, also has corners, a circumference and a half-etched section at the lower edge along its circumference. A leadframe is also provided with a plurality of tie bars. Each of the tie bars has a side surface and a bottom surface. The plurality of tie bars are connected to the corners of the chip paddle. The plurality of the tie bars externally extend from the chip paddle and have a half-etched section. A plurality of dam bars are provided on the leadframe help limit flow of encapsulation material on the leadframe. A plurality of leads, referred to alternately as internal or external, connect to the leadframe. Each of the leads has a side surface and a bottom surface. The leads are radially formed at regular intervals along and spaced apart from the circumference to the chip paddle and extend towards the chip paddle. Each of the leads has a step shaped half-etched section facing the chip paddle. A plurality of conductive wires, comprised of a suitable conductor, are electrically connected to and between the plurality of leads and the semiconductor chip. Encapsulating or encapsulant material encapsulates the semiconductor chip, conductive wires, chip paddle, and the leads to form a package body. The flow of the encapsulation material is limited by the dam bars formed on the leadframe. The dam bars also serve to stabilize the leads on the leadframe. After encapsulation, the chip paddle, leads, and tie bars are externally exposed at respective side and bottom surfaces.
The above described assembly further includes, in accordance with the present invention, at least one depression formed on the externally exposed bottom surface of the leads to improve the solder joint strength with a motherboard. Alternately and additionally, at least one depression may be formed on the externally exposed bottom surface of the leads. Likewise, at least one depression may be formed on the externally exposed bottom surface of at least one tie bar to increase the solder joint strength. The presence of the depressions in the respective locations of the semiconductor package serves to provide an additional area which may fuse with the solder, thereby strengthening the solder joint strength between the semiconductor package and the motherboard.